SPICE Model
PDK
Standard Cell
Chip-level HBM ESD Analysis Platform
Accurate simulation of HBM discharge paths, providing accuracy and speed with nonlinear simulation technology and TLP models
Facilitating layout extraction, identifies pads and ESD protection devices, and generates reduced-order models for parasitic layout resistances
Simulating pad-to-pad HBM strikes, mapping IR-drops and current densities
Identifying overstressed internal-circuit devices, incorrect or missing ESD cells, addressing issues like excessive voltages, electromigration, and imbalanced current distribution
Simulation based approach
for high level accuracy
Industry-leading
ESD-verification tools
All HBM-stress conditions
for ESD sign-off before tape out
Highlights marginal devices
to avoid costly field failures
Covering metallization and
internal circuit sneak-path checks
Low cost set up, useful
in all stages of the design flow
HBM ESD analysis
for AMS chips
HBM ESD analysis
for automotive chips
HBM ESD analysis
for PMICs
HBM ESD analysis
for digital chips
